Many computer processors utilize a fixed system clock that can be subdivided to form a processor clock. The processor clock is generally derived by means that allow it to be stretched in whole system clock cycle time increments. When the processor accesses an asynchronous operation, the processor clock is stretched until an asynchronous data valid signal is received. Because the system clock frequency is fixed, the processor clock must continue to be stretched after receipt of the data valid signal until it is synchronized to the system clock through two stages of synchronizing flip-flops. After synchronization, the processor clock resumes its normal frequency. However, the period of time required for synchronization of the processor clock constitutes wasted time.
A major design factor for a data driven clock is that the clock generator should not waste time synchronizing to an external input. In a computer processor, there is always a minimum cycle period that must be met. During data transfer if a data valid signal is not received by the end of the minimum cycle period, then the cycle must be stretched until the data valid signal is received. To prevent wasted time from unnecessary processor clock stretching, each clock cycle should be tested and stretched on an individual basis.
Basic free-running oscillator circuits are well-known means for stretching processor clock cycles on an individual basis. Such an oscillator circuit is illustrated and described in conjunction with FIG. 1 of U.S. Pat. No. 4,691,121 to Theus, which is hereby incorporated by reference. However, such basic oscillator circuits are sensitive to changes, instabilities, and noise in the data valid signal. This sensitivity results in instabilities and delays in reestablishing the processor clock cycle after it has been stretched. Therefore, there is a need for a simple oscillator circuit that functions as a data driven clock generator which can stretch the processor clock on a cycle-by-cycle basis and which is insensitive to instabilities in the data valid signal. Such a clock generator should allow a data valid signal to stabilize without wasting time in reestablishing the normal processor clock cycle.